How is the chip-level security of an loT device achieved?

Chip-level security, also known as hardware security, involves protecting the device at the silicon level. The JTAG (Joint Test Action Group) interface is a powerful hardware-level debugging port that can provide direct access to a device's memory and processor. If left unsecured, it can be used by attackers to extract firmware, bypass security controls, or inject malicious code. Securing this interface, for example by disabling it in production units, requiring authenticated access, or encrypting the communication, is a fundamental practice for achieving chip-level security and preventing physical attacks.

B. Keeping a device on a flat network is a network architecture decision, not a chip-level security measure. It generally increases risk.
C. Closing insecure network services is a software or firmware hardening technique, operating at a higher level than the silicon chip itself.
D. Changing the password of a router is a network security measure, external to the IoT device's own hardware security.

1. Grand, J. (2004). Practical secure hardware design for embedded systems. In Proceedings of the 2004 ACM workshop on Embedded systems security (pp. 61-68). https://doi.org/10.1145/1028622.1028632 (Discusses the importance of securing physical interfaces like JTAG as part of hardware security design).

2. O'Flynn, C. (2014). The Hardware Hacking Handbook: Breaking Embedded Security with Hardware Attacks. No Starch Press. (Chapter 5, "JTAG," details how JTAG interfaces are exploited and methods for securing them at the hardware level).

3. Kammerstetter, M., Platzer, C., & Kastner, W. (2012). Security analysis of JTAG/boundary scan. In 2012 IEEE 17th International Conference on Emerging Technologies & Factory Automation (ETFA 2012) (pp. 1-8). https://doi.org/10.1109/ETFA.2012.6489619 (This paper provides a detailed analysis of JTAG vulnerabilities and countermeasures).